Fixed typo in TargetConfigs.scala Chipyard Mixins authored by Farzad Fatollahi-Fard's avatar Farzad Fatollahi-Fard
......@@ -3,12 +3,13 @@ title: BXE FireSim Documentation - Building Hardware
version: v2.2.0
firesim:
version: main
url: https://github.com/firesim/firesim/tree/c301eb5
docs-url: https://docs.fires.im/en/main/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Building-a-FireSim-Bitstream/Xilinx-Alveo-U250.html
url: 'https://github.com/firesim/firesim/tree/c301eb5'
docs-url: >-
https://docs.fires.im/en/main/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Building-a-FireSim-Bitstream/Xilinx-Alveo-U250.html
chipyard:
version: main
url: https://github.com/ucb-bar/chipyard/tree/85d2620
doc-url: https://chipyard.readthedocs.io/en/main/
url: 'https://github.com/ucb-bar/chipyard/tree/85d2620'
doc-url: 'https://chipyard.readthedocs.io/en/main/'
aro-cn: D2021-2106030006
---
......@@ -190,7 +191,7 @@ We have now completed configuring FireSim. The `TARGET_CONFIG` section is the sp
## Creating a Design with Chipyard Mixins
Chipyard allows us to use their library of standard architecture and hardware components to build designs. These are called _Mixins_, and the list of components is out of scope for this tutorial. For now, we'll just use these to design a dual-core Rocket core.
Let's add our design to the list of designs available to FireSim. Open `$CHIPYARD_ROOT/generators/firechip/src/main/scala/TargetConfigs.scala` and add the following to the end of the file:
Let's add our design to the list of designs available to FireSim. Open `$CHIPYARD_ROOT/generators/firechip/chip/src/main/scala/TargetConfigs.scala` and add the following to the end of the file:
```scala
// BXE FireSim Dual-Core Rocket
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