Building-Hardware.md

 ---
 title: BXE FireSim Documentation - Building Hardware
-version: v2.0.0
+version: v2.2.0
 firesim:
-  version: a78040a
-  url: https://github.com/firesim/firesim/tree/a78040a
-  docs-url: https://docs.fires.im/en/stable/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Building-a-FireSim-Bitstream/Xilinx-Alveo-U250.html
+  version: main
+  url: https://github.com/firesim/firesim/tree/c301eb5
+  docs-url: https://docs.fires.im/en/main/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Building-a-FireSim-Bitstream/Xilinx-Alveo-U250.html
 chipyard:
-  version: 766ea73
-  url: https://github.com/ucb-bar/chipyard/tree/766ea73
-  doc-url: https://chipyard.readthedocs.io/en/stable/
+  version: main
+  url: https://github.com/ucb-bar/chipyard/tree/85d2620
+  doc-url: https://chipyard.readthedocs.io/en/main/
 aro-cn: D2021-2106030006
 ---
 
@@ -54,7 +54,7 @@ build_farm:
     #     - "222.222.2.222":
     #         override_build_dir: /scratch/specific-build-host-build-dir
     build_farm_hosts:
-        - wilson.lbl.gov
+        - localhost
 
 ```
 
@@ -95,7 +95,7 @@ build_farm:
       #         - "222.222.2.222":  
       #                 override_build_dir: /scratch/specific-build-host-build-dir  
       build_farm_hosts:
-          - wilson.lbl.gov
+          - localhost
 
 builds_to_run:
     # this section references builds defined in config_build_recipes.yaml
@@ -188,7 +188,7 @@ alveo_u250_firesim_rocket_dualcore_nic:
 We have now completed configuring FireSim. The `TARGET_CONFIG` section is the specific design in Chipyard we'd like to build. However, this design doesn't exist in Chipyard...
 
 ## Creating a Design with Chipyard Mixins
-Chipyard allows us to use their library of standard architecture and hardware components to build designs. These are called *Mixins*, and the list of components is out of scope for this tutorial. For now, we'll just use these to design a dual-core Rocket core.
+Chipyard allows us to use their library of standard architecture and hardware components to build designs. These are called _Mixins_, and the list of components is out of scope for this tutorial. For now, we'll just use these to design a dual-core Rocket core.
 
 Let's add our design to the list of designs available to FireSim. Open `$CHIPYARD_ROOT/generators/firechip/src/main/scala/TargetConfigs.scala` and add the following to the end of the file:
 
@@ -207,16 +207,16 @@ And that's it! We're ready to build our design!
 ## Generating a Bitstream
 With the FireSim build environment and Chipyard design configured, we're ready to launch the build. With FireSim loaded into our environment (`source sourceme-manager.sh --skip-ssh-setup`), we can launch a build.
 
-```bash
+```shell
 cd $FIRESIM_ROOT
 # source sourceme-manager.sh --skip-ssh-setup
-firesim buildbitstream
+firesim buildbitstream -r -r ${CY_DIR}/sims/firesim-staging/sample_config_build_recipes.yaml
 ```
 
 As stated before, this may take **MANY HOURS** to complete. Grab yourself a cup of your favorite beverage and let the machine build. You should see the following successful build message when done:
 
 ```
-[wilson.lbl.gov] out: 
+[localhost] out: 
 xilinx_alveo_u250/
 xilinx_alveo_u250/metadata
 xilinx_alveo_u250/firesim.bit
@@ -267,23 +267,21 @@ target_config:
 ## Running the Simulation
 We can now run the design and boot Linux on this design. Following the tutorial from before:
 
-```bash
+```shell
 cd $FIRESIM_ROOT
-firesim launchrunfarm
-firesim infrasetup
-firesim runworkload
+firesim infrasetup -a ${CY_DIR}/sims/firesim-staging/sample_config_hwdb.yaml -r ${CY_DIR}/sims/firesim-staging/sample_config_build_recipes.yaml
+firesim runworkload -a ${CY_DIR}/sims/firesim-staging/sample_config_hwdb.yaml -r ${CY_DIR}/sims/firesim-staging/sample_config_build_recipes.yaml
 ```
 
-In a seperate window:
+In a separate window, log into the runner machine and run:
 
-```bash
+```shell
 screen -r fsim0
 ```
 
-
 Wait for the console to boot, then verify multiple cores in the booted simulation:
 
-```
+```shell
 # cat /proc/cpuinfo 
 processor       : 0
 hart            : 1
@@ -307,12 +305,12 @@ mimpid          : 0x20181004
 Congratulations! You have now simulated a dual-core RISC-V Rocket Core and booted Linux on an FPGA! :champagne: :champagne: :champagne:
 
 # Building BlackBox Designs
-Chipyard is capable of wrapping custom Verilog designs into a [BlackBox](https://chipyard.readthedocs.io/en/stable/Customization/Incorporating-Verilog-Blocks.html). This allows you to use your custom Verilog designs as accelerators attached to the core, or as the core itself.
+Chipyard is capable of wrapping custom Verilog designs into a [BlackBox](https://chipyard.readthedocs.io/en/main/Customization/Incorporating-Verilog-Blocks.html). This allows you to use your custom Verilog designs as accelerators attached to the core, or as the core itself.
 
-FireSim has an example using a single-core [CVA6 RISC-V Verilog](https://chipyard.readthedocs.io/en/stable/Generators/CVA6.html) implemenation.
+FireSim has an example using a single-core [CVA6 RISC-V Verilog](https://chipyard.readthedocs.io/en/main/Generators/CVA6.html) implemenation.
 
 ---
 
 [^1]: This research is based upon work supported by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA), through the Advanced Graphical Intelligence Logical Computing Environment (AGILE) research program, under Army Research Office (ARO) contract number D2021-2106030006. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of the ODNI, IARPA, ARO, or the U.S.  Government.
 
-[^2]: [Chipyard](https://chipyard.readthedocs.io/en/stable/) is a framework for designing and evaluating full-system hardware using agile teams. It is composed of a collection of tools and libraries designed to provide an integration between open-source and commercial tools for the development of systems-on-chip.
+[^2]: [Chipyard](https://chipyard.readthedocs.io/en/main/) is a framework for designing and evaluating full-system hardware using agile teams. It is composed of a collection of tools and libraries designed to provide an integration between open-source and commercial tools for the development of systems-on-chip.