Building-Hardware.md

@@ -221,6 +221,23 @@ As stated before, this may take **MANY HOURS** to complete. Grab yourself a cup
 [localhost] out: [16:23:12] Run vpl: FINISHED. Run Status: impl Complete!
 [localhost] out: INFO: [v++ 60-1441] [16:23:12] Run run_link: Step vpl: Completed
 [localhost] out: Time (s): cpu = 00:07:56 ; elapsed = 07:02:18 . Memory (MB): peak = 2218.742 ; gain = 0.000 ; free physical = 14228 ; free virtual = 29502
+
+... More Vitis Output ...
+
+[localhost] out:
+FireSim FPGA Build Completed
+Your bitstream has been created!
+Add
+
+vitis_firesim_rocket_dualcore_no_nic:
+    xclbin: /home/bxeuser/firesim/deploy/build_dir//platforms/vitis/cl_FireSim-FireSimDualRocketMMIOOnlyConfig-BaseVitisConfig/bitstream/build_dir.xilinx_u250_gen3x16_xdma_4_1_202210_1/firesim.xclbin
+    deploy_triplet_override: FireSim-FireSimDualRocketMMIOOnlyConfig-BaseVitisConfig
+    custom_runtime_config: null
+
+to your config_hwdb.yaml to use this hardware configuration.
+Build complete! Vitis bitstream ready. See /home/bxeuser/firesim/deploy/built-hwdb-entries/vitis_firesim_rocket_dualcore_no_nic.
+The full log of this run is:
+/home/bxeuser/firesim/deploy/logs/2023-05-05--00-25-06-buildbitstream-1OSMVEVQTQSX2648.log
 ```
 
 When complete, you'll find a bitstream in your build directory: `/home/bxeuser/firesim/deploy/build_dir//platforms/vitis/cl_FireSim-FireSimDualRocketMMIOOnlyConfig-BaseVitisConfig/bitstream/build_dir.xilinx_u250_gen3x16_xdma_4_1_202210_1/firesim.xclbin`