Building-Hardware.md

@@ -15,7 +15,7 @@ This work was funded by the iARPA AGILE Project. [^1]
 
 [[_TOC_]]
 
-# Building a Dual-Core Rocket with Chipyard
+# Building a Dual-Core Rocket
 
 In this example, we will be modifying FireSim to generate a dual-core RISC-V Rocket Core (`vitis_firesim_rocket_dualcore_no_nic`) and booting it up on the attached FPGA. Generating bitstreams for the Alveo U250 can take a **few hours** to complete, so it's recommended to do your work in a [persistent session](home#opening-a-persistent-session-on-bxe-firesim-nodes).
 
@@ -228,7 +228,79 @@ When complete, you'll find a bitstream in your build directory: `/home/bxeuser/f
 This is important for when we want to run the simulation. Speaking of which...
 
 # Running a Custom Design
+Now that the build is complete, we need to tell FireSim that this design is available to be run. We'll add `vitis_firesim_rocket_dualcore_no_nic` to FireSim's hardware database, then configure the simulation to use the new design.
 
+## `~/firesim/deploy/config_hwdb.yaml`
+Using the path generated in the build step, we add an entry to the hardware database. Add the following to the end of the file:
+
+```yaml
+vitis_firesim_rocket_dualcore_no_nic:
+    xclbin: /home/bxeuser/firesim/deploy/build_dir//platforms/vitis/cl_FireSim-FireSimDualRocketMMIOOnlyConfig-BaseVitisConfig/bitstream/build_dir.xilinx_u250_gen3x16_xdma_4_1_202210_1/firesim.xclbin
+    deploy_triplet_override: FireSim-FireSimDualRocketMMIOOnlyConfig-BaseVitisConfig
+    custom_runtime_config: null
+```
+
+## `~/firesim/deploy/config_runtime.yaml`
+Now we're ready to deploy this design in the simulation. We modify this file to tell FireSim what the target design we're going to simulate. In the `target_config` section, change the `default_hw_config` to point to our new design, `vitis_firesim_rocket_dualcore_no_nic`. It should resemble this:
+
+```yaml
+target_config:
+    topology: no_net_config
+    no_net_num_nodes: 1
+    link_latency: 6405
+    switching_latency: 10
+    net_bandwidth: 200
+    profile_interval: -1
+    default_hw_config: vitis_firesim_rocket_dualcore_no_nic
+    plusarg_passthrough: ""
+```
+
+## Running the Simulation
+We can now run the design and boot Linux on this design. Following the tutorial from before:
+
+```bash
+cd ~/firesim
+firesim launchrunfarm
+firesim infrasetup
+firesim runworkload
+```
+
+In a seperate window:
+
+```bash
+screen -r fsim0
+```
+
+
+Wait for the console to boot, then verify multiple cores in the booted simulation:
+
+```
+# cat /proc/cpuinfo 
+processor       : 0
+hart            : 1
+isa             : rv64imafdckph
+mmu             : sv39
+uarch           : sifive,rocket0
+mvendorid       : 0x0
+marchid         : 0x1
+mimpid          : 0x20181004
+
+processor       : 1
+hart            : 0
+isa             : rv64imafdckph
+mmu             : sv39
+uarch           : sifive,rocket0
+mvendorid       : 0x0
+marchid         : 0x1
+mimpid          : 0x20181004
+```
+
+Congratulations! You have now simulated a dual-core RISC-V Rocket Core and booted Linux on an FPGA! :champagne: :champagne: :champagne:
+
+# Building BlackBox Designs
+Chipyard is capable of wrapping custom Verilog designs into a [BlackBox](https://chipyard.readthedocs.io/en/stable/Customization/Incorporating-Verilog-Blocks.html). This allows you to use your custom Verilog designs as accelerators attached to the core, or as the core itself.
+
+FireSim has an example using a single-core [CVA6 RISC-V Verilog](https://chipyard.readthedocs.io/en/latest/Generators/CVA6.html) implemenation.
 
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